Design and Verification Conference & Exhibition
DVCon 2003
February 24-26, 2003
DoubleTree Hotel, San Jose, CA
Website:  http://www.dvcon.org

DVCon (formerly known as HDLcon) is the premier conference on the usage
of Hardware Description Languages (HDLs) and Hardware
Verification Languages (HVLs) for the design and verification
of electronic systems and integrated circuits.  

REGISTRATION IS NOW OPEN!!!  SPECIAL DISCOUNT!
This is your opportunity to attend the conference and exhibition,
network with your peers, test drive the newest tools and learn the
latest developments with HDLs to keep you ahead of your competition.  
  Register by December 1st and receive $50.00 off
  your registration fee. (Tutorials not included)
Full conference registration includes access to the Technical Sessions,
Exhibit Hall, Monday and Tuesday Luncheons, Monday Night Cocktail
Reception, sponsored by Mentor Graphics, Corp., and CD-Rom Proceedings. 

To register for the conference, you may register on-line, via mail or
fax. Visit the web site: http://www.dvcon.org.  If you have any
questions, contact Kathy MacLennan at kathy@mpassociates.com or call
303-530-4562.

HOTEL RESERVATIONS - DEADLINE: JANUARY 23, 2003
Discounted conference room rate is $165 Single/Double.
Availability is limited, and we encourage you to make your reservations
as soon as possible.  Reservations may be made by contacting the hotel
directly at 408-453-4000.

TECHNICAL PROGRAM
This year DVCon is featuring over 35 papers, 3 panel sessions, and a
Monday Luncheon Keynote, "Design for Verification" presented by Aart De
Geus, CEO, Synopsys, Inc.
  Panels:  Methodology Driving Language, or Vice Versa
           Verilog & Assertions - Do they Mix?
Tuesday Luncheon Presentation:  Updates on the SystemC Standard

The full technical program details will be available on the web site
November 22nd.  Our speakers and panelists are leading experts in their
respective fields and will deliver valuable insights into design
strategies and methodologies.  

TUTORIALS!! Wednesday, February 26, 2003
1).  Practical Verilog for Chip-level Verification 
2).  Functional Verification with Specman Elite, Step-by-Step
3).  Finding More Bugs with VERA's Contraint-Driven
         Stimulus Generation
4).  The Sugar 2.0 Property Specification Language 
5).  Transaction-based Modeling and Verificaiton with SystemC
6).  An Introduction to Smart Verification Using SystemVerilog
7).  The Design Flow - Linking Design, Verification, and Common 
            Sense to Build Chips that Work

EXHIBITS 
In no other venue will you see such a comprehensive and focused offering
of HDL tools and solutions.  Visit the web site for a complete listing
of participating vendors. Be sure to join us at the annual cocktail
reception in the Exhibit Hall, sponsored by Mentor Graphics, Corp. on
Monday, February 24th from 5:00pm-7:00pm.  

Exhibit Hours:
Monday, February 24th:  12pm-7pm
Tuesday, February 25th:  9am-12pm

We look forward to seeing you at DVCon 2003, February
24-26, 2003 at the DoubleTree Hotel San Jose.

Sincerely,

Frank Weiler           Stuart Sutherland
General Chair          Program
Chair**********************************************************************
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